U.S. Pat. Nos. 4,636,942 and 4,754,398 disclose tight-coupling communication schemes for use in interprocessor communication in a multiprocessor system. These tight-coupling communication schemes provides a set of shared registers which may be accessed by the CPUs at rates commensurate with intra-CPU operation. The shared registers thus provide a fast inter-CPU communication path to minimize overhead for multi-tasking of small tasks with frequent data interchange. The scheme also provides that tasks may be coupled through the shared memory in the multiprocessor system, as accomplished in conventional interprocessor communication schemes. These patents also disclose a scheme in which tile shared registers are organized to provide N+1 "clusters", where N equals the number of processors in the system. Processors are allowed access to the shared registers according to which cluster they are assigned to. A semaphore register in each cluster provides means for synchronizing access to the clusters between the processors. The entire disclosure of each of the above-identified patents are hereby incorporated herein by reference. Further information on the basic concept outlined above may be had with respect to these patents.